In magnetic tape digital storage systems it has been proposed to provide error detection and correction for successive blocks of digital information by the use of a parity check bit for each parallel byte of information, and an additional byte of error correction information calculated from the information bits in the block of data. A widely used error correction configuration and circuitry for its implementation are disclosed in an article entitled Magnetic Tape Coding, by A. M. Patel and S. J. Hong, IBM Journal of Research and Development, pages 579-588, Nov. 1974.
In the system described in the above-identified article, seven bytes of basic information with each data byte including eight bits of information, are initially provided on a parallel basis. A simple parity bit is then provided for each data byte, so that we now have seven groups of nine bits each to be recorded on the tape. An eighth, nine-bit error correction "byte" is then formed as a polynomial function of the other seven "bytes", and the eighth byte is recorded on the tape to complete the group.
To form the eighth byte, the article cited above discloses, in FIG. 7 thereof, the use of an eight stage feedback shift register having "Exclusive OR" circuits interconnecting each stage of the shift register and at the output thereof, and with the output of the last stage of the shift register coupled back to the first stage thereof, and to the Exclusive OR circuits at the input to the fourth, fifth, and sixth stages of the shift register. Incidentally, an Exclusive OR circuit is defined as a logic circuit which provides an output when an odd number of its inputs are energized.
The respective bits of each of the successive bytes of input data are applied to the Exclusive OR circuits, along with the output from the prior stage of the shift register and the feedback digital signal from the output of the last stage of the shift register, with this last mentioned feedback signal only going to some of the Exclusive OR circuits. Following the receipt of the seven successive bytes of information from each block of data, the output from the eight shift register stages forms an error check code, ECC, which is added as the eighth byte to the previous seven bytes of data. A simple parity check bit is added to each of the eight bytes to give eight "bytes" of nine bits each which may either be applied to the nine track tape directly or following conversion to a run-length limited code.
When digital information is taken off the tape, each nine bit "byte" is checked for parity, giving an eight bit parity "vector", for the eight byte block of binary digits. If this parity vector entirely O's, this would give a preliminary indication that there were no errors, actually that there was not an even number of errors in any one of the eight bytes of transferred information. The error correction code forming the eighth byte of the corrected code may then be recalculated from the first seven transmitted bytes and subtracted from the transmitted eighth ECC byte, or each bit of the two bytes is applied to an Exclusive OR circuit, to confirm that there is no error, if this error "syndrome" is zero.
Now, if the parity vector and/or the error syndrome is not all zeros, some errors are apparently present in the block of data.
The system as described in the article cited above is capable of correcting errors in two tracks of data, with these tracks having been identified by pointers in accordance with known techniques, by determining the phase shift of recorded data, or other techniques. Complicated circuitry including a shift register and a series of Exclusive OR gates may then be employed, as described in the above-identified article, to obtain correction vectors for each of the two tracks in error, and these tracks can then be corrected.
Shortcomings with the system as described above and in the conventional hardware implementations thereof, include the very large number of integrated circuits, normally more than 500, which are used in the system implementation. The cost of such systems is necessarily high and the weight of such prior art systems is usually over ninety pounds.
It has also been proposed to implement the encoding and decoding steps of the hardware by microcomputer circuitry, which follows the hardware implementation on a step-by-step basis. However, the hardware steps involving the successive Exclusive OR, and shift register operations, and including many conditional operations, is very time-consuming when accomplished by a microcomputer; and such circuitry normally cannot and does not correct errors in a continuous, on-line basis.
Accordingly, principal objects of the present invention involve reducing the number of components, and the size and weight of the components, and the size and weight of the complete tape drive system, and accomplishing error correction functions on a real-time, on-line basis.